Web Reference: I am facing an issue with the post-synthesis implementation of a special Serial-In-Serial-Out kind of buffer. It receives inputs and stores them in registers and can later output the stored inputs.... Nov 7, 2023 · For synthesis, Vivado likely expects the loop to execute a constant number of times, but your for loop uses a variable delay_cycles in the start condition. You declared a counter variable, but did not use it. You could implement a counter instead of using the for loop. This is due to the use of a "string" datatype in the SystemVerilog design. Although "string" is a supported datatype of SystemVerilog, it is not synthesizable in Vivado. To resolve this, there are two choices of edits that can be made: Add quotes around ROM_TYPE in the signal declaration line: (* rom_style="ROM_TYPE"*) With quotes, synthesis will see it as a string, and the design passes synth ...
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