Web Reference: Figure 16 shows the rules to be followed in CMOS well processes to accommodate both n and p transistors. Figure 16: CMOS design rules. In this process all the spacing between each layers and dimensions will be in terms micrometer. The 2^m here represents the feature size. CMOS 'λ' Design Rules : The MOSIS stands for MOS Implementation Service is the IC fabrication service available to universities for layout, simulation, and test the completed designs. 3D fabrication process simulator with cross sectional viewer. Step-by-step 3-D visualization of fabrication for any portion of layout.
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